NAND-type flash memory devices are in great demand for their high storage capacity and high integration density, without a need for refreshing, and their straightforward electrical functions of erasing and programming. The facilities of data retention of the NAND flash memory device, even during a power-off, are very useful for portable electronic systems such as mobile computers, digital still cameras, or PDAs.
The NAND flash memory device has memory cells electrically erased and programmed, i.e., EEPROM cells, each being formed of a source and a drain spaced apart from each other in a bulk region (or a semiconductor substrate), a floating gate positioned over a channel region between the source and drain, and a control gate over the floating gate. Insulation films are interposed between the control and floating gates, and between the floating gate and the channel region.
FIG. 1 shows an arrangement of a memory cell array including the EEPROM cells. Memory cell transistors M15˜MC0 connected in series form a cell string CS0 (or CS1). The memory cell transistor MC15 is connected to bitline BL0 (or BL1) through string selection transistor SST, and the memory cell transistor MC0 is connected to common source line CSL through ground selection transistor GST. Control gates of the memory cell transistors M15 arranged in a row are coupled to wordline WL15. In the same manner, control gates of other cell transistors in a row are coupled to their corresponding wordlines.
Threshold voltages of the cell transistors are set at about −3V by erasing, and then a programming operation is carried out for a selected memory cell transistor to raise its threshold voltage. This is done by applying a high voltage of 20V to a corresponding wordline coupled to the selected cell transistor. Threshold voltages of the other non-selected cell transistors do not change from their current values. However, typically a programming disturbance occurs whereby memory cell transistors coupled to a wordline coupled to a selected memory cell transistor are undesirably programmed by the high-leveled program voltage even though the cell transistors are not selected in a programming operation.
A program inhibit technique for preventing the non-selected memory cell transistors from being undesirably programmed has been proposed in U.S. Pat. No. 5,677,873 entitled “Method of programming flash EEPROM integrated circuit memory devices to prevent inadvertent programming of nondesignated NAND memory cells therein”, or U.S. Pat. No. 5,991,202 entitled “Method for reducing program disturb during self-boosting in a NAND flash memory”. In a method of program inhibition called self-boosting, a current path towards a ground is cut off by applying 0V to a gate of the ground selection transistor GST. 0V is applied to a bitline (e.g., BL0) assigned to a selected memory cell transistor while a non-designated bitline (e.g., BL1) sees a program inhibit voltage of 3.3V or 5V of a power supply voltage VCC.
At the same time, the power supply voltage VCC is applied to a gate of the string selection transistor SST so that a source of the string selection transistor is charged up to VCC-Vth (Vth is a threshold voltage of the string selection transistor). The string selection transistor is substantially shut off. Next, a high program voltage Vpgm and a pass voltage Vpass are applied to a selected wordline and non-selected wordlines, respectively, so that channel voltages of the non-selected memory cell transistors are boosted up to levels that prevent programming. The boosted channel voltages prohibit generation of F-N tunneling between the floating gate and channel region, preventing any change of the non-selected memory cell transistors from their primary erased states.
Nevertheless, there is still a problem of programming disturbance, because the non-selected memory cell transistors adjacent to a selected memory cell transistor tend to be programmed due to leakage current flowing through parasitic MOS (meal-oxide-semiconductor) transistors 10 as shown in FIG. 1. The parasitic transistors 10 are connected between active regions (sources or drains) of cell transistors coupled to the same wordlines.
Referring to FIG. 2 which shows a sectional diagram taken along the line A-A′ of FIG. 1, channel region 2 of program cell transistor MC14p (to be programmed) and channel region 3 of program-inhibit cell transistor MC14i act as a source and a drain, respectively, of the parasitic transistor. And the wordline W14 acts as a gate of the parasitic transistor. A substrate region under field oxide 14 between the channel regions 2 and 3 is assigned to a channel region of the parasitic transistor. As a result, if the program voltage Vpgm is higher than a threshold voltage of the parasitic transistor, the parasitic transistor will be turned on, inducing a generation of leakage current flowing into the channel region 2 of the program cell transistor MCI 4p from the channel region 3 of the program-inhibit cell transistor MC14i through the conductive parasitic transistor. Thus, the self-boosted voltage at the channel region 2 of the program-inhibit cell transistor MC14i becomes lower, resulting in an undesirable programming disturbance.
There is a way to overcome the aforementioned problem by increasing the threshold voltage of the parasitic MOS transistor, using an ion implantation into the substrate region acting as the channel region of the parasitic transistor. However, it is preferred to restrict such an ion implantation into the substrate region because of a decrease in breakdown voltage in the drain region, or because of a scaling-down of a topological size of the memory cell array. Increasing the threshold voltage of the parasitic transistor by biasing the substrate 1 with a negative voltage is also not desirable because a longer time for charging the substrate 1 increases overall program time.